LIBRARY ieee;
USE ieee.std_logic_1164.all;	--for STD_LOGIC_VECTOR
use ieee.math_real.all; 		-- for UNIFORM, TRUNC
use ieee.numeric_std.all; 		-- for TO_UNSIGNED

ENTITY RandomNumberGenerator IS
	PORT(
			Clock	:IN		STD_LOGIC
		);
END RandomNumberGenerator;


ARCHITECTURE behavior of RandomNumberGenerator is
	BEGIN PROCESS(Clock)
		-- Seed values for random generator
		variable seed1, seed2: positive;
		-- Random real-number value in range 0 to 1.0
		variable rand: real;
		-- Random integer value in range 0..4095
		variable int_rand: integer;
		-- Random 12-bit stimulus
		variable stim: std_logic_vector(11 downto 0);
		begin
			-- initialise seed1, seed2 if you want -
			seed1 := 1;
			seed2 := 2;
			--rand  := 0.5;
			-- otherwise they're initialised to 1 by default
			loop -- testbench stimulus loop?
			--rand := 
			--UNIFORM(seed1, seed2, rand);
			-- get a 12-bit random value...
			-- 1. rescale to 0..(nearly)4096, find integer part
			int_rand := INTEGER(TRUNC(rand*4096.0));
			-- 2. convert to std_logic_vector
			stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
		end loop;
	end process;
end behavior;			